Non-volatile memory elements are capable of storing binary data, and retaining the stored memory data even when not powered by from power source. Non-volatile memory typically finds applications in memory structures directed to long-term or permanent storage of data, which may not be consistently connected to a power source. Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100 which may be utilized in a non-volatile memory structure. The STT-MRAM bit cell 100 includes a storage element (MTJ 105), a switching element (transistor 101), a bit line 102 and a word line 103. The MTJ storage element is formed, for example, from at least two ferromagnetic layers (a pinned layer and a free layer), each of which can hold a magnetic field or polarization, separated by a thin non-magnetic insulating layer (tunneling barrier). Electrons from the two ferromagnetic layers can penetrate through the tunneling barrier due to a tunneling effect under a bias voltage applied to the ferromagnetic layers. The spin polarized electrons tunneling through to the free layer may transfer their torque or angular momentum to the magnetic elements of the free layer, thus affecting the magnetic polarization of the free layer.
The magnetic polarization of the free layer can be reversed so that the polarity of the pinned layer and the free layer are either substantially aligned (parallel) or opposite (anti-parallel). The resistance of the electrical path through the MTJ will vary depending on the alignment of the polarizations of the pinned and free layers. This variance in resistance can be used to program and read the bit cell 100. The STT-MRAM bit cell 100 also includes a source line 104, a sense amplifier 108, read/write circuitry 106 and a bit line reference 107. Read/write circuitry 106 includes fixed strength write drivers (not shown) for the bit line 102 and source line 104. It will be appreciated that the operation and construction of the memory cell 100.
For example, the bit cell 100 may be programmed such that a binary value “1” is associated with an operational state wherein the polarity of the free layer is parallel to the polarity of the pinned layer. Correspondingly, a binary value “0” may be associated with an anti-parallel orientation between the two ferromagnetic layers. A binary value may thus be written to the bit cell by changing the polarization of the free layer. A sufficient current density (typically measured in Amperes/centimeter2) generated by the electrons flowing across the tunneling barrier is required to change the polarization of the free layer. The current density required to switch the polarization of the free layer is also called switching current density. Decreasing the value of the switching current density leads to beneficially lowering the power consumption of the MTJ storage elements.
However, conventional techniques to lower the switching current density may adversely impact the thermal stability of the MTJ storage element. An MTJ storage element with low thermal stability may be unable to retain the data value written to the storage element (or storage cell), and further, cells with low thermal stability are easy to write. Such easily-writeable cells (also called “easy cells”) are also susceptible to “read disturbs”. Read disturbs occur when a value of “1” written to a cell, switches to “0” during a read operation, because the conventionally low current values for a read operation on an MTJ storage element are comparable and of same polarity as the current density required to write a “0” on an easy cell.
For the foregoing reasons, there is a need to appropriately decrease the current density for write operations on easy cells, while targeting a net reduction in current consumption in order to reduce power consumption of the STT-MRAM array. Conventional techniques lack the ability to detect cells that are easy to write. Further, conventional fixed strength write drivers are not programmable, and the drive strength cannot be varied in accordance with the write-ability of the cells.